• DocumentCode
    1964551
  • Title

    Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs

  • Author

    Tsukamoto, Y. ; Kida, T. ; Yamaki, T. ; Ishii, Y. ; Nii, K. ; Tanaka, K. ; Tanaka, S. ; Kihara, Y.

  • Author_Institution
    Renesas Electron. Corp., Tokyo, Japan
  • fYear
    2011
  • fDate
    19-21 Sept. 2011
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    We discuss dynamic stability for single-port SRAM that manifests itself in the difference between minimum operating voltage (Vmin) for longer and shorter word-line (WL) pulse width (Twl). The most probable failure points (MPFPs) that determine Vmin for various Twl are investigated. Regarding dual-port SRAM, we identify the MPFP for the worst Vmin degraded by WL pulse skew between ports in asynchronous operation. The validity of our simulation results are verified through comparison with measured data for SRAM modules in 28 nm generation.
  • Keywords
    SRAM chips; SRAM modules; asynchronous operation; dual-port SRAM; dynamic stability; minimum operating voltage; most probable failure points; single-port SRAM; size 28 nm; word-line pulse width; Bit rate; Circuit stability; Clocks; Random access memory; Simulation; Stability analysis; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference (CICC), 2011 IEEE
  • Conference_Location
    San Jose, CA
  • ISSN
    0886-5930
  • Print_ISBN
    978-1-4577-0222-8
  • Type

    conf

  • DOI
    10.1109/CICC.2011.6055314
  • Filename
    6055314
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1964551