DocumentCode :
1964589
Title :
A 7.2 mW 75.3 dB SNDR 10 MHz BW CT delta-sigma modulator using Gm-C-based noise-shaped quantizer and digital integrator
Author :
Taewook Kim ; Changsok Han ; Maghari, Nima
Author_Institution :
Univ. of Florida, Gainesville, FL, USA
fYear :
2015
fDate :
17-19 June 2015
Abstract :
A 3rd order continuous-time delta-sigma modulator using a Gm-C based noise-shaped integrating quantizer (NSIQ) with a digital back-end integrator is presented in this paper. By incorporating the back-end digital integrator, the conventional tradeoff between resolution and speed in time-based quantization is alleviated. Therefore by using only three clock edges and a low-power Gm-C, effective 4-bit quantization is achieved which also provides first order noise-shaping. The zero-crossing comparator is replaced by a preamplifier and three latches. The proposed modulator was fabricated in a 0.13μm CMOS process with an active area of 0.08mm2. It operates at 640 MHz and achieves a peak SNDR of 75.3 dB and a peak SFDR of 94.1 dB in a 10 MHz bandwidth while consuming 7.2 mW from a 1.2V power supply.
Keywords :
CMOS integrated circuits; comparators (circuits); delta-sigma modulation; 3rd order continuous-time delta-sigma modulator; CMOS process; Gm-C based noise-shaped integrating quantizer; digital back-end integrator; digital integrator; frequency 640 MHz; power 7.2 mW; size 0.13 mum; time-based quantization; voltage 1.2 V; zero-crossing comparator; Clocks; Latches; Linearity; Modulation; Noise shaping; Quantization (signal); Signal to noise ratio;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
Type :
conf
DOI :
10.1109/VLSIC.2015.7231279
Filename :
7231279
Link To Document :
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