Title :
1.8 Mbit/mm2 ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology
Author :
Tsukamoto, Yasumasa ; Morimoto, Masao ; Yabuuchi, Makoto ; Tanaka, Miki ; Nii, Koji
Author_Institution :
Renesas Electron. Corp., Tokyo, Japan
Abstract :
A new bit-cell (BC) layout for ternary content-addressable memory (TCAM) is developed in a 16 nm Fin-FET process. The proposed BC is 15.8% smaller than the conventional BC. We design a 10kb TCAM macro which achieves the highest density of 1.8 Mbit/mm2. Measurement shows that total active power in our proposed macro is 8% less than that in the conventional one. A 484 ps of search access time is observed at 0.8 V, which marks the world fastest operation cycle of 1.25 G search per second at this time.
Keywords :
CMOS integrated circuits; MOSFET; content-addressable storage; FinFET bulk CMOS technology; bit-cell layout; search access time; size 16 nm; storage capacity 10 Kbit; ternary content-addressable memory; ternary-CAM macro; time 484 ps; voltage 0.8 V; Arrays; Layout; Power demand; Power measurement; Proposals; Random access memory; Semiconductor device measurement; 16-nm; Bit-cell layout; Fin-FET; TCAM;
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
DOI :
10.1109/VLSIC.2015.7231286
