DocumentCode
1964794
Title
A 0.7V 810µW 10b 30MS/s comparator-based two-step pipelined ADC
Author
Lee, Ho-Young ; Gubbins, David ; Lee, Bumha ; Moon, Un-Ku
Author_Institution
Sch. of EECS, Oregon State Univ., Corvallis, OR, USA
fYear
2011
fDate
19-21 Sept. 2011
Firstpage
1
Lastpage
4
Abstract
This paper presents a 10b 30MS/s comparator-based two-step pipelined ADC that uses a comparator instead of an opamp to reach low-voltage and low-power operation with a rail-to-rail input. This implementation also incorporates a digital offset calibration scheme in the comparator. The prototype ADC, fabricated in a 0.13μm CMOS process, consumes 810μW at 0.7V supply and achieves 121fJ FOM at 10MHz input frequency.
Keywords
CMOS digital integrated circuits; analogue-digital conversion; calibration; comparators (circuits); low-power electronics; radiofrequency integrated circuits; CMOS process; comparator-based two-step pipelined ADC; digital offset calibration scheme; frequency 10 MHz; low-power operation; low-voltage operation; opamp; power 810 muW; rail-to-rail input; size 0.13 mum; voltage 0.7 V; word length 10 bit; Accuracy; Arrays; Calibration; Capacitance; Capacitors; Prototypes; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference (CICC), 2011 IEEE
Conference_Location
San Jose, CA
ISSN
0886-5930
Print_ISBN
978-1-4577-0222-8
Type
conf
DOI
10.1109/CICC.2011.6055326
Filename
6055326
Link To Document