• DocumentCode
    1964962
  • Title

    A fault tolerant hierarchical interconnection network and its bandwidth analysis

  • Author

    Mahmud, Syed Masud ; Samaratunga, L. Tissa

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Wayne State Univ., Detroit, MI, USA
  • Volume
    2
  • fYear
    1995
  • fDate
    19-21 Apr 1995
  • Firstpage
    736
  • Abstract
    A number of hierarchical interconnection networks (HINs) has been proposed in the literature which can be used for building large cluster-based multiprocessors. It is very desirable that a HIN must be fault tolerant, because even a single fault in the network can completely disconnect a large number of processors and memory modules from the rest of the system. As a result, the performance of the system will decrease significantly. In this paper, we have proposed a HIN which can work under faulty conditions but with a slight degradation in performance. We have also developed analytical models to determine the performance of the proposed fault tolerant HIN. The analytical models have been validated by simulation models
  • Keywords
    digital simulation; fault tolerant computing; multiprocessor interconnection networks; bandwidth analysis; cluster-based multiprocessors; fault tolerant hierarchical interconnection network; memory modules; simulation models; Analytical models; Bandwidth; Communication switching; Degradation; Fault tolerance; Fault tolerant systems; Hierarchical systems; Multiprocessing systems; Multiprocessor interconnection networks; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Algorithms and Architectures for Parallel Processing, 1995. ICAPP 95. IEEE First ICA/sup 3/PP., IEEE First International Conference on
  • Conference_Location
    Brisbane, Qld.
  • Print_ISBN
    0-7803-2018-2
  • Type

    conf

  • DOI
    10.1109/ICAPP.1995.472261
  • Filename
    472261