Title :
Broadwell: A family of IA 14nm processors
Author :
Nalamalpu, Ankireddy ; Kurd, Nasser ; Deval, Anant ; Mozak, Chris ; Douglas, Jonathan ; Khanna, Ashish ; Paillet, Fabrice ; Schrom, Gerhard ; Phelps, Boyd
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
Intel Core™ M and 5th generation of Core™ processors (code named Broadwell) are fabricated on an optimized 14 nm process technology node resulting in a 49% reduction in feature-neutral die area. 14nm created a new optimized process flavor for Core™ M to improve energy efficiency for mobile devices. Techniques and optimizations were implemented to deliver 2.5x TDP reduction coupled with up-to 60% higher graphics performance. New process technology combined with various design techniques reduced the minimum voltage of operation by 50 m V. Broadwell introduces the second generation of Fully Integrated Voltage Regulator with better droop control and parallel boot LVR along with other power-reduction features resulting in 35% reduction in active and standby power over first generation. 3DL inductor technology introduced for the first time in Broadwell, enables 30 % reduction in package thickness and improved low-load efficiency. IO re-partitioning of the SOC and a major re-design of DDR system resulted in 30% reduction in I/O power. Shutting down various parts of the SOC die in various idle states (C* states) resulted in 60% reduction in the idle power. New software controlled co-optimization methods were implemented such as duty-cycle control and dynamic display support to improve the energy efficiency of the graphics and the display subsystem.
Keywords :
circuit optimisation; hardware-software codesign; integrated circuit design; low-power electronics; microprocessor chips; voltage regulators; Broadwell processors; IA processor family; Intel Core M; SOC repartitioning; display subsystem; droop control; duty cycle control; dynamic display support; feature neutral die; fifh generation Core processors; fully integrated voltage regulator; graphics subsystem; mobile device energy efficiency; parallel boot LVR; power reduction; software controlled cooptimization methods; Graphics; Inductors; Optimization; Program processors; Rails; Regulators; Voltage control;
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
DOI :
10.1109/VLSIC.2015.7231304