Author :
Yang, S.H. ; Sheu, J.Y. ; Ieong, M.K. ; Chiang, M.H. ; Yamamoto, T. ; Liaw, J.J. ; Chang, S.S. ; Lin, Y.M. ; Hsu, T.L. ; Hwang, J.R. ; Ting, J.K. ; Wu, C.H. ; Ting, K.C. ; Yang, F.C. ; Liu, C.M. ; Wu, I.L. ; Chen, Y.M. ; Chent, S.J. ; Chen, K.S. ; Cheng,
Abstract :
An industry leading 28nm high-performance mobile SoC technology featuring metal-gate/high-k process is presented. The technology is optimized to offer wide power-to-performance transistor dynamic range and highest wired gate density with superior low-R/ELK interconnects, critical for next generation mobile computing/SOC applications. Through process and design optimization, historical trend is maintained for gate density and SRAM cell sizes. Variations control strategy through process and design collaboration is also described.
Keywords :
CMOS integrated circuits; mobile communication; system-on-chip; SRAM cell sizes; high performance mobile applications; metal gate high K CMOS SoC technology; size 28 nm; wide power to performance transistor dynamic range; wired gate density; CMOS integrated circuits; High K dielectric materials; Logic gates; Metals; Mobile communication; Random access memory; Transistors;
