Title :
Impact of Resistive-Bridging Defects in SRAM Core-Cell
Author :
Fonseca, R. Alves ; Dilillo, L. ; Bosio, A. ; Girard, P. ; Pravossoudovitch, S. ; Virazel, A. ; Badereddine, N.
Author_Institution :
Lab. d´´Inf., de Robot. et de Microelectron. de Montpellier, Univ. de Montpellier II, Montpellier, France
Abstract :
In this paper, we present a study on the effects of resistive-bridging defects in the SRAM core-cell. The position of the resistive-bridges has been chosen taking in account an actual industrial core-cell layout. We have performed an extensive number of simulations, varying the resistance value of the defects, supply voltage, frequency and temperature. Experimental results show malfunctions not only within the defective core-cell, but also in other core-cells (defect-free) of the memory array. Static and dynamic faults, single-cell and double-cells faults have been found.
Keywords :
SRAM chips; fault simulation; integrated circuit layout; logic arrays; SRAM core cell; core cell layout; double cells fault; dynamic fault; memory array; resistive bridging defects; single cell fault; static fault; Electronic equipment testing; Frequency; Hardware; Information analysis; Parasitic capacitance; Random access memory; Robots; Temperature distribution; Uniform resource locators; Voltage; SRAM; core-cell; resistive-bridging defects;
Conference_Titel :
Electronic Design, Test and Application, 2010. DELTA '10. Fifth IEEE International Symposium on
Conference_Location :
Ho Chi Minh City
Print_ISBN :
978-0-7695-3978-2
Electronic_ISBN :
978-1-4244-6026-7
DOI :
10.1109/DELTA.2010.31
