A 13 b 40 MSample/s CMOS pipelined folding ADC with background offset trimming

The folding/interpolating ADC exhibits a distinct trait attributed by folder zero-crossing error and gain mismatch, which appear in general as an INL error. It is of paramount interest to control the zero-crossings accurately so that they can be spaced evenly to cover the whole conversion range. The folder zero-crossing errors collectively result from folder offset, reference error, tail-current mismatch, interpolation error, etc. In CMOS, the poor offset of the differential pair as well as other process uncertainty have resulted in the performance much poorer than the bipolar counterpart. This CMOS folding/interpolating ADC operates with 13 b linearity at bipolar folder speed.