A self-trimming 14b 100MSample/s CMOS DAC

A 14b 100MSample/s CMOS DAC in 0.35 /spl mu/m CMOS achieves high static and dynamic linearity. The static linearity is obtained by a background self-trimming circuit which guarantees 14b INL/DNL. The dynamic linearity is obtained by the use of a track/attenuate stage at the DAC output. Maximum dynamic linearity is attained up to 100MSample/s update rate, but functionality is retained up to 200MSample/s. Power consumption from 3.3 V is 180 mW at 100MSample/s and 210 mW at 200MSample/s.