Title :
An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology
Author :
Amara, Amara ; Giraud, Bastien ; Thomas, Olivier
Author_Institution :
LISITE Lab., Inst. Super. d´´Electron. de Paris (I.S.E.P.), Paris, France
Abstract :
This paper presents a new SRAM memory cell in Double Gate MOS technology. It´s a reconfigurable 6T-4T that takes benefit of the advantages of both 6T and 4T SRAM cells. The cell improves both read stability and write-ability, without adding any transistor or external signal, compared to conventional 6T SRAM cell. The write ability is improved by a factor of 64% and the stability in read mode by a factor of 70% while slightly increasing the stability in retention mode. Thanks to its excellent stability and good insensitivity to process variations (¿/¿ 4 and 2 times lower), the proposed architecture is also a promising candidate for low voltage applications.
Keywords :
MOSFET; MOSFET circuits; SRAM chips; circuit stability; low-power electronics; 6T hybrid SRAM memory cell; double-gate MOS technology; low voltage applications; read stability; retention mode stability; write-ability; Electrostatics; FinFETs; Fluctuations; Low voltage; MOSFETs; Paper technology; Random access memory; Stability; Threshold voltage; Transistors; Fully Depleted SOI (FD-SOI); Planar Double-Gate (DG); SRAM cell; Ultra Low Voltage (ULV); read and write tradeoffs;
Conference_Titel :
Electronic Design, Test and Application, 2010. DELTA '10. Fifth IEEE International Symposium on
Conference_Location :
Ho Chi Minh City
Print_ISBN :
978-0-7695-3978-2
Electronic_ISBN :
978-1-4244-6026-7
DOI :
10.1109/DELTA.2010.54