A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology

Author

Gangasani, Gautam R. ; Hsu, Chun-Ming ; Bulzacchelli, John F. ; Rylov, Sergey ; Beukema, Troy ; Freitas, David ; Kelly, William ; Shannon, Michael ; Qi, Jieming ; Xu, Hui H. ; Natonio, Joseph ; Rasmus, Todd ; Guo, Jong-Ru ; Wielgos, Michael ; Garlett, Jon

Author_Institution

IBM Syst. & Technol. Group, Hopewell Junction, NY, USA

fYear

2011

fDate

19-21 Sept. 2011

Firstpage

1

Lastpage

4

Abstract

This paper presents a 16-Gb/s 45-nm SOI CMOS transceiver for multi-standard backplane applications. The receiver uses a 12-tap DFE with circuit refinements for supporting higher data rates. Both the receiver and the transmitter use dynamic adaptation to combat parameter drift due to changing supply and temperature. A 3-tap FFE is included in the source-series-terminated driver. The combination of DFE and FFE permits error-free NRZ signaling at 16-Gb/s over channels exceeding 30dB loss. The 8-port core with two PLLs is fully characterized for 16GFC and consumes 385 mW/link.

Keywords

CMOS integrated circuits; decision feedback equalisers; driver circuits; phase locked loops; silicon-on-insulator; transceivers; 12-tap current integrating DFE; 3-tap FFE; PLL; SOI CMOS technology; bit rate 16 Gbit/s; circuit refinement; combat parameter drift; error-free NRZ signaling; loss 30 dB; multistandard backplane transceiver; size 45 nm; source-series-terminated driver; timing drift; voltage offset dynamic adaptation; CMOS integrated circuits; Clocks; Computer architecture; Decision feedback equalizers; Switches; Timing; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2011 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4577-0222-8

Type

conf

DOI

10.1109/CICC.2011.6055366

Filename

6055366