A 12b 70MS/s SAR ADC with digital startup calibration in 14nm CMOS

A 12b 70MS/s sub-2 radix SAR ADC designed on Intel´s 14nm tri-gate CMOS process is presented. It utilizes a startup calibration for correcting capacitor mismatches in its CDAC. The calibration is fully digital and doesn´t require accurate references or input signals. The sub-2 radix architecture provides redundancy that improves speed. The comparator has a novel preamplifier that helps achieve low-noise and high-speed operation. The ADC achieves 68.1dB SNDR, 80dB SFDR, 70MS/s speed, and consumes 4.3mW power.