Notations for Multiphase Pipelines

FPGAs, (Field-Programmable Gate Arrays) are often used for embedded image processing applications. Parallelism, and in particular pipelining, is the most suitable architecture for supporting the required high throughput. Although pipelining is a well known technique for hardware design and is simple to describe, our experience has been that people have many problems implementing working pipelines, especially for multiphase designs. Existing hardware description languages force developers to design pipelines as a special case of parallel architecture, which makes it difficult to ensure that the pipeline has internally consistent timing. This is especially problematic in multiphase pipelines. This paper shows how many of these problems may be overcome by basing the notation on sequential dataflow, and discusses control issues of priming, stalling and flushing, with a proposed compiler implementation.