Title :
A 12-bit 200-MS/s 3.4-mW CMOS ADC with 0.85-V supply
Author :
Mathew, Joseph Palackal ; Long Kong ; Razavi, Behzad
Author_Institution :
Univ. of California, Los Angeles, Los Angeles, CA, USA
Abstract :
A SAR ADC incorporates two VCOs and a TDC as a multi-bit quantizer to improve the conversion speed. Using background calibration and realized in 45-nm technology, the ADC exhibits an SNDR of 68 dB and an FOM of 8 fJ/conv. step at Nyquist.
Keywords :
CMOS digital integrated circuits; calibration; time-digital conversion; voltage-controlled oscillators; CMOS ADC; FOM; Nyquist; SAR ADC; SNDR; TDC; VCO; analog-digital converters; background calibration; figure of moment; multibit quantizer; power 3.4 mW; size 45 nm; voltage 0.85 V; voltage-controlled oscillators; Ash; Calibration; Capacitors; Delays; Semiconductor device measurement; Very large scale integration; Voltage-controlled oscillators;
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
DOI :
10.1109/VLSIC.2015.7231330
