DocumentCode
1965690
Title
An Efficient Hardware Implementation for a Reciprocal Unit
Author
Habegger, Andreas ; Stahel, Andreas ; Goette, Josef ; Jacomet, Marcel
Author_Institution
MicroLab, Bern Univ. of Appl. Sci., Biel-Bienne, Switzerland
fYear
2010
fDate
13-15 Jan. 2010
Firstpage
183
Lastpage
187
Abstract
The computation of the reciprocal of a numerical value is an important ingredient of many algorithms. We present a compact hardware architecture to compute reciprocals by two or three Newton-Raphson iterations to obtain the accuracy of IEEE 754 single- and double-precision standard, respectively. We estimate the initialization value by a specially designed second-order polynomial approximating the reciprocal. By using a second-order polynomial, we succeed in using one single hardware architecture for both, the polynomial approximation computations as well as the Newton-Raphson iterations. Therefore, we obtain a most compact hardware implementation for the complete reciprocal computation.
Keywords
IEEE standards; Newton-Raphson method; computer architecture; polynomial approximation; IEEE 754; Newton-Raphson iterations; hardware architecture; hardware implementation; numerical value; polynomial approximation; reciprocal unit; second-order polynomial; Approximation algorithms; Computer architecture; Convergence; Delay; Hardware; Iterative algorithms; Iterative methods; Newton method; Polynomials; Table lookup; Arithmetic inversion; Nelder-Mead; Newton-Raphson; hardware algorithm; polynomial initialization; reciprocal;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Design, Test and Application, 2010. DELTA '10. Fifth IEEE International Symposium on
Conference_Location
Ho Chi Minh City
Print_ISBN
978-0-7695-3978-2
Electronic_ISBN
978-1-4244-6026-7
Type
conf
DOI
10.1109/DELTA.2010.65
Filename
5438691
Link To Document