Title :
A 1 GHz single-issue 64 b PowerPC processor
Author :
Hofstee, P. ; Aoki, N. ; Boerstler, D. ; Coulman, P. ; Dhong, S. ; Flachs, B. ; Kojima, N. ; Kwon, O. ; Lee, K. ; Meltzer, D. ; Nowka, K. ; Park, J. ; Peter, J. ; Posluszny, S. ; Shapiro, M. ; Silberman, J. ; Takahashi, O. ; Weinberger, B.
Author_Institution :
IBM Austin Res. Lab., TX, USA
Abstract :
This 64 b single-issue PowerPC processor contains 19M transistors and is fabricated in 0.12 /spl mu/m L/sub eff/ six-layer copper interconnect CMOS. Nominal processor clock frequency is 1.0 GHz. At the fast end of the process distribution the processor reaches 1.15 GHz (1.87 V, 101/spl deg/C, 112 W). As in a previous design, nearly the entire processor is implemented using delayed-reset and self-resetting dynamic circuit macros. New contributions include: (1) a fully pipelined, four execution-stage IEEE double-precision floating-point unit (FPU) with fused multiply-add. 2) Sum-addressed memory management units (MMUs) and 64 kB 2-cycle caches. (3) Support for the full 64 b PowerPC instruction set. (4) Dynamic PLA-based control. (5) A microarchitecture and floorplan that balances critical paths. (6) Delayed-reset dynamic circuits that support stress testing (burn-in). 7) Improved clock generation and distribution.
Keywords :
CMOS digital integrated circuits; copper; floating point arithmetic; microprocessor chips; pipeline processing; very high speed integrated circuits; 1 to 1.15 GHz; 1.87 V; 112 W; 2-cycle caches; 64 bit; 64 kB; Cu; IEEE double-precision FPU; PowerPC instruction set support; clock distribution; clock generation; delayed-reset dynamic circuit macros; dynamic PLA-based control; floating-point unit; four execution-stage; fully pipelined architecture; fused multiply-add; memory management units; self-resetting dynamic circuit macros; single-issue PowerPC processor; six-layer Cu interconnect CMOS process; sum-addressed MMUs; CMOS process; Circuit testing; Clocks; Copper; Delay; Energy management; Frequency; Integrated circuit interconnections; Memory management; Stress control;
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-5853-8
DOI :
10.1109/ISSCC.2000.839705
