32-nm SOI programmable, high-bandwidth 8.0-GHz digital PLL

A digital phase-locked loop (PLL) to filter clock jitter in source-synchronous serial link applications is presented. The PLL achieves bandwidth programmability from 20 to 300 MHz while allowing for a maximum input frequency of 4 GHz. An improved resolution bang-bang phase detector and a double-regulated, supply-insensitive VCO mitigate extreme noise environments. The PLL is designed in 32-nm SOI technology and operates on 1.2-volt nominal supply, consuming 20 mW power.