32-nm SOI programmable, high-bandwidth 8.0-GHz digital PLL

Author

Maheshwari, Sanjeev K. ; Fang, Emerson ; Aggarwal, Sanjeev

Author_Institution

AMD, Inc., Sunnyvale, CA, USA

fYear

2011

fDate

19-21 Sept. 2011

Firstpage

1

Lastpage

4

Abstract

A digital phase-locked loop (PLL) to filter clock jitter in source-synchronous serial link applications is presented. The PLL achieves bandwidth programmability from 20 to 300 MHz while allowing for a maximum input frequency of 4 GHz. An improved resolution bang-bang phase detector and a double-regulated, supply-insensitive VCO mitigate extreme noise environments. The PLL is designed in 32-nm SOI technology and operates on 1.2-volt nominal supply, consuming 20 mW power.

Keywords

clocks; digital phase locked loops; jitter; microwave filters; phase detectors; silicon-on-insulator; voltage-controlled oscillators; SOI programmable high-bandwidth digital PLL; bandwidth 20 MHz to 300 MHz; bandwidth 8.0 GHz; digital phase-locked loop; double-regulated supply-insensitive VCO; extreme noise mitigation; filter clock jitter; frequency 4 GHz; maximum input frequency; power 20 mW; resolution bang-bang phase detector; size 32 nm; source-synchronous serial link application; voltage 1.2 V; Bandwidth; Clocks; Detectors; Frequency modulation; Jitter; Phase locked loops; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2011 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4577-0222-8

Type

conf

DOI

10.1109/CICC.2011.6055386

Filename

6055386