Title :
A More Precise Model of Noise Based PCMOS Errors
Author :
Bhanu, Arun ; Lau, Mark S K ; Ling, Keck-Voon ; Mooney, Vincent J., III ; Singh, Anshul
Author_Institution :
Inst. for Sustainable Nanoelectron., NTU, Singapore, Singapore
Abstract :
In this paper we present a new model for characterization of probabilistic gates. While still not mainstream, probabilistic CMOS has the potential to dramatically reduce energy consumption by trading off with error rates on individual bits, e.g., least significant bits of an adder. Our contribution helps account for the filtering effect seen in noise based PCMOS in a novel way. The characterization proposed here can enable accurate multi-bit models based on fast mathematical extrapolation instead of expensive and slow HSPICE simulations.
Keywords :
CMOS integrated circuits; error statistics; extrapolation; probability; HSPICE simulation; energy consumption; error rates; fast mathematical extrapolation; multi-bit models; noise based PCMOS errors; probabilistic CMOS; probabilistic gates; Adders; Boolean functions; CMOS logic circuits; Circuit noise; Mathematical model; Probabilistic logic; Semiconductor device modeling; Semiconductor device noise; Signal to noise ratio; Voltage;
Conference_Titel :
Electronic Design, Test and Application, 2010. DELTA '10. Fifth IEEE International Symposium on
Conference_Location :
Ho Chi Minh City
Print_ISBN :
978-0-7695-3978-2
Electronic_ISBN :
978-1-4244-6026-7
DOI :
10.1109/DELTA.2010.18
