Title :
A 60 mW 10 b CMOS image sensor with column-to-column FPN reduction
Author :
Sugiki, T. ; Ohsawa, S. ; Miura, H. ; Sasaki, M. ; Nakamura, N. ; Inoue, I. ; Hoshino, M. ; Tomizawa, Y. ; Arakawa, T.
Author_Institution :
Toshiba Corp., Kanagawa, Japan
Abstract :
A 60 mW 10b 660(H)/spl times/490(v) pixel digital CMOS image sensor with column-to-column FPN reduction introduces the double inverting amplifier with double clamp circuit for reduction of column-to-column fixed pattern noise (dark FPN and light FPN). It operates with a 3.3 V power supply and has 60 mW power consumption. This sensor is uses 0.6 /spl mu/m, triple-poly-silicon, double-metal CMOS technology.
Keywords :
CMOS image sensors; integrated circuit noise; 0.6 micron; 10 bit; 3.3 V; 490 pixel; 60 mW; 660 pixel; column-to-column fixed pattern noise; digital CMOS image sensor; double clamp circuit; double inverting amplifier; CMOS image sensors; Circuits; Clamps; Delay; Energy consumption; Latches; Pixel; Signal processing; Threshold voltage; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-5853-8
DOI :
10.1109/ISSCC.2000.839712
