• DocumentCode
    1966073
  • Title

    Dual-Output Stacked Class-EE Power Amplifiers in 45nm SOI CMOS for Q-Band Applications

  • Author

    Chakrabarti, Anandaroop ; Sharma, Jahnavi ; Krishnaswamy, Harish

  • Author_Institution
    Dept. of Electr. Eng., Columbia Univ., New York, NY, USA
  • fYear
    2012
  • fDate
    14-17 Oct. 2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Stacking multiple devices improves the output power and efficiency in mmWave power amplifiers by increasing the achievable output voltage swing. This work presents a new topology for stacked Class-E-like power amplifiers. In this technique, a Class-E load network is placed at the drain node of each stacked device, which imparts a true Class-E behavior to all the devices in the stack. The resulting topology is called the Dual (Multi) Output Stacked Class-EE PA. Two Q-band prototypes - a unit cell with 2 devices stacked, and a power-combined version employing two such unit cells - have been fabricated in IBM´s 45nm SOI CMOS technology using the 56nm body-contacted devices. Measurements yield a peak PAE of 25.5% for the Dual Output Stacked Class-EE unit cell with saturated output power of 17.9 dBm, and a peak PAE >;16% for the power-combined version with saturated output power >;19.1 dBm. Excellent correspondence is observed between simulation and measurement as a consequence of active and passive device modeling efforts.
  • Keywords
    CMOS analogue integrated circuits; field effect MIMIC; integrated circuit modelling; millimetre wave power amplifiers; network topology; silicon-on-insulator; IBM SOI CMOS technology; Q-band applications; active device modeling; body-contacted devices; class-E behavior; class-E load network; drain node; dual-output stacked class-EE power amplifiers; efficiency 25.5 percent; mm-wave power amplifiers; multioutput stacked class-EE PA; passive device modeling; power-combined version; size 45 nm; size 56 nm; stacked class-E power amplifier topology; unit cell; voltage swing; CMOS integrated circuits; CMOS technology; Integrated circuit modeling; Power generation; Power measurement; Switches; Transmission line measurements;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Compound Semiconductor Integrated Circuit Symposium (CSICS), 2012 IEEE
  • Conference_Location
    La Jolla, CA
  • ISSN
    1550-8781
  • Print_ISBN
    978-1-4673-0928-8
  • Type

    conf

  • DOI
    10.1109/CSICS.2012.6340107
  • Filename
    6340107