Investigation of a novel self-aligned dual gate MOSFET structure

The dual-gate approach to MOSFET scaling has been proposed for some time as a method of obtaining increased drive current, with potential simulated I/sub d/ values well in excess of twice that of single gate devices. In reality, approaches to fabricating such devices have suffered from an inability to align the two gates. Dual gate alignment is critical as the overlap capacitance is responsible for a large fraction of the gate delay due to the Miller effect. Alignment tolerance issues mean that the bottom gate of such a structure must be significantly oversized, and this contributes enormously to the delay through increased overlap capacitance. In this paper, a method for fabricating a dual-gate SOI MOSFET is proposed, which involves using ion cut techniques (Bruel, Electron. Lett. vol. 31, p. 1201, 1995) to bare the MOS for buried gate transistor underside processing, the use of a transparent quartz ´handle´ wafer to which the delaminated structure is adhered, the use of the (now) bottom gate electrode as a hard mask for near-field lithography of the top gate, and using through-wafer illumination by g-line light to expose the poly resist. The paper presents an experimental feasibility study, as well as simulation studies to show that it is possible to expose through such a transistor stack and obtain alignment between top and bottom gates. This is then tested experimentally on patterned structures, and it is shown that it is indeed possible to obtain dual-gate alignments on repeated poly lines-and-spaces structures, with 0.3 /spl mu/m gates and 0.7 /spl mu/m spacings.