Title :
A 1V 13mW frequency-translating ΔΣ ADC with 55dB SNDR for a 4MHz band at 225MHz
Author :
Chopp, Philip M. ; Hamoui, Anas A.
Author_Institution :
McGill Univ., Montreal, QC, Canada
Abstract :
A frequency-translating ΔΣ ADC is fabricated in 1V 65nm CMOS for use in digital-IF receivers. Its bandpass ΔΣ architecture uses single-path mixing inside the ΔΣ loop to downconvert a 4MHz input band from 225MHz (IF1) to 25MHz (IF2). It achieves an SNDR of 55dB, while consuming only 13mW. This low power is realized by sampling at a frequency lower than IF1, and by noise-shaping primarily at IF2.
Keywords :
CMOS integrated circuits; delta-sigma modulation; nanoelectronics; receivers; ΔΣ loop; CMOS; bandpass ΔΣ architecture; bandwidth 4 MHz; digital-IF receivers; frequency 225 MHz; frequency-translating ΔΣ ADC; noise figure 55 dB; noise-shaping; voltage 1 V; CMOS integrated circuits; Filtering; Frequency modulation; Mixers; Resonant frequency; Timing;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2011 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4577-0222-8
DOI :
10.1109/CICC.2011.6055393
