Title :
An Envelope-Tracking CMOS-SOS Power Amplifier with 50% Overall PAE and 29.3 dBm Output Power for LTE Applications
Author :
Hassan, Muhammad ; Olson, Chris ; Kovac, Dave ; Yan, Jonmei J. ; Nobbe, Dan ; Kelly, Dylan ; Asbeck, Peter M. ; Larson, Lawrence E.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of California at San Diego, La Jolla, CA, USA
Abstract :
This paper presents a CMOS envelope tracking power amplifier for LTE band-13 (782 MHz) applications. The envelope amplifier is implemented in 0.18 μm bulk CMOS process while the RF power amplifier is designed in 0.35 μm CMOS Silicon-on-Sapphire (SOS) technology. To overcome low breakdown voltage limit of MOSFETs, a stacked FET structure is used. The complete envelope tracking system achieves an overall PAE of 50% for 16 QAM, 10 MHz LTE signal with 6.6 dB peak-to-average ratio (PAPR), while delivering 29.3 dBm output power. A memory-less digital pre-distortion (DPD) is employed to linearize the overall system, which pushes ACLR down to -46.5 dBc.
Keywords :
CMOS analogue integrated circuits; MOSFET; UHF field effect transistors; UHF integrated circuits; UHF power amplifiers; quadrature amplitude modulation; silicon-on-insulator; ACLR; CMOS envelope tracking power amplifier; CMOS silicon-on-sapphire technology; LTE applications; MOSFET low breakdown voltage limit; PAE; PAPR; QAM; RF power amplifier; bulk CMOS process; efficiency 50 percent; envelope-tracking CMOS-SOS power amplifier; frequency 10 MHz; frequency 782 MHz; memory-less DPD; memory-less digital predistortion; peak-to-average ratio; size 0.18 mum; size 0.35 mum; stacked FET structure; CMOS integrated circuits; CMOS technology; Peak to average power ratio; Power amplifiers; Power generation; Radio frequency; Switches;
Conference_Titel :
Compound Semiconductor Integrated Circuit Symposium (CSICS), 2012 IEEE
Conference_Location :
La Jolla, CA
Print_ISBN :
978-1-4673-0928-8
DOI :
10.1109/CSICS.2012.6340110
