The vertical replacement-gate (VRG) process for scalable general-purpose complementary logic

A major challenge in scaling metal-oxide-semiconductor field-effect transistors (MOSFETs) is controlling the gate length, L/sub G/. Variable L/sub G/ leads to variable current drive, requiring conservative digital designs, and to device mismatch that makes the fastest transistors unusable in precision analog designs. The vertical, replacement-gate (VRG) process uses the thickness of a deposited film to precisely define the gate length, while preserving the small gate overlap capacitances and shallow, self-aligned source/drain extensions that are critical to modern MOSFETs. In brief, a silicon device pillar is grown through a multilayer sandwich, whose center layer is later removed and replaced by the gate, and whose upper and lower layers provide dopants for the source/drain extensions. The gate dielectric can be thin, high-quality, thermal SiO/sub 2/ grown on [100]-oriented single-crystal silicon. Previous vertical MOSFET schemes inherently result in poor gate length control, high gate overlap capacitances, or low-quality gate oxides. The first VRG-MOSFETs are competitive with optimized short-channel planar MOSFETs. L/sub G/=200 nm (L/sub ch//spl Gt/190 nm) VRG-n MOSFETs have I/sub on/=1.1 mA//spl mu/m with I/sub off/=11 pA//spl mu/m (and subthreshold swing s=76 mV/dec).