Title :
Low power and error resilient PN code acquisition filter via statistical error compensation
Author :
Kim, Eric P. ; Baker, Daniel J. ; Narayanan, Sriram ; Jones, Douglas L. ; Shanbhag, Naresh R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
Abstract :
We present a 256-tap PN code acquisition filter in an 180nm CMOS process employing statistical system-level error compensation. Under voltage overscaling (VOS), near constant detection probability (Pdet) above 90% with 5.8× reduction in energy is achieved at a supply voltage 27% below the point of first failure (PoFF) with an error rate (pe) of 0.868. This is an improvement of 5.8× in energy-efficiency over conventional error free designs and 3.79× in energy-efficiency and 2170× in error tolerance over existing error tolerant designs.
Keywords :
CMOS integrated circuits; statistics; CMOS process; energy-efficiency over conventional error free designs; error rate; error resilient PN code acquisition filter; near constant detection probability; size 180 nm; statistical error compensation; statistical system-level error compensation; supply voltage; voltage overscaling; Computer architecture; Correlation; Error analysis; Error compensation; Semiconductor device measurement; Solid state circuits; Timing;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2011 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4577-0222-8
DOI :
10.1109/CICC.2011.6055397
