Title :
A 0.4–1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit
Author :
Bongjin Kim ; Kundu, Somnath ; Kim, Chris H.
Author_Institution :
Dept. of ECE, Univ. of Minnesota, Minneapolis, MN, USA
Abstract :
A 0.4-1.6GHz spur-free bang-bang PLL (BBPLL) is demonstrated in a 65nm CMOS process where a standard D-flip/flop (DFF) based frequency subtractor is used in lieu of a conventional divider, for down-converting the feedback clock frequency. The inherent first-order noise-shaping property allows the proposed frequency subtraction circuit to mitigate spur-noise issues found in conventional digital BBPLLs. The fabricated BBPLL including a 10bit ring-DCO circuit has an in-band phase noise of -97dBc/Hz at 100kHz and an integrated RMS jitter (from 20kHz to 2MHz) of 2.8ps while consuming 2.7mW at 1.6GHz and occupying 0.019mm2. The PLL circuit has an FoM of -226.7dB.
Keywords :
CMOS logic circuits; feedback; flip-flops; integrated circuit noise; jitter; microwave integrated circuits; oscillators; phase locked loops; BBPLL; CMOS process; D-flip-flop; DFF; FoM; PLL circuit; digitally controlled oscillators; feedback clock frequency; figure of moment; first-order noise-shaping property; frequency 0.4 GHz to 1.6 GHz; frequency 100 kHz; frequency 20 kHz to 2 MHz; frequency subtraction circuit; frequency subtractor circuit; in-band phase noise; integrated RMS jitter; power 2.7 mW; ring-DCO circuit; size 0.019 mm; size 65 nm; spur-free bang-bang digital PLL; spur-noise; Clocks; Frequency control; Frequency conversion; Noise shaping; Phase locked loops; Phase noise; Standards;
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
DOI :
10.1109/VLSIC.2015.7231355
