DocumentCode :
1966226
Title :
A 450-fs jitter PVT-robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells
Author :
Mina Kim ; Seojin Choi ; Jaehyouk Choi
Author_Institution :
Ulsan Nat. Inst. of Sci. & Technol., Ulsan, South Korea
fYear :
2015
fDate :
17-19 June 2015
Abstract :
This paper presents a PVT-robust, low-jitter, injection-locked clock multiplier with the frequency resolution of one tenth of the reference frequency, using a DLL-based PVT-calibrator. As the key idea, the ring-VCO and the DLL consist of identical delay cells and share the control voltage. Since the DLL continually corrects the delay of the unit delay cells, the degradation of jitter due to the drift of the free-running VCO frequency can be prevented. The RMS-jitter was 448 fs, and its variation with temperature was regulated to be less than ± 4%.
Keywords :
calibration; clocks; delay lock loops; injection locked oscillators; jitter; multiplying circuits; voltage-controlled oscillators; DLL-based PVT-calibrator; PVT-robust low-jitter injection-locked clock multiplier; RMS-jitter; control voltage; delay cells; free-running VCO frequency; jitter degradation; ring-VCO; time 448 fs; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits (VLSI Circuits), 2015 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-86348-502-0
Type :
conf
DOI :
10.1109/VLSIC.2015.7231356
Filename :
7231356
Link To Document :
بازگشت