Title :
An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface
Author :
Mishra, Navin K. ; Jain, Manish ; Le, Phuong ; Mukherjee, Sanku ; Sendhil, Arul ; Amirkhany, Amir
Author_Institution :
Rambus Chip Technol., Bangalore, India
Abstract :
A bi-modal x32 memory interface supports 6.4-Gbps GDDR5 signaling as well as 2.4-Gbps DDR3 signaling with a 1.5V IO supply. The interface incorporates a novel driver and pre-driver structure that supports one-tap equalization and presents very small capacitive loading to the pins. The entire interface, including both data and request channels achieves 11.6mW/Gbps and 27.7mW/Gbps energy efficiencies in GDDR5 and DDR3 modes respectively, and communicates successfully with 1.6-Gbps DDR3 and 6.0-Gbps GDDR5 DRAMs.
Keywords :
DRAM chips; DDR3 signaling; DRAM; GDDR5 signaling; IO supply; bimodal memory interface; bit rate 2.4 Gbit/s; bit rate 6.4 Gbit/s; capacitive loading; energy efficiency; one-tap equalization; predriver structure; voltage 1.5 V; Calibration; Capacitors; Clocks; Graphics; Impedance; Random access memory; Transistors;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2011 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4577-0222-8
DOI :
10.1109/CICC.2011.6055399
