• DocumentCode
    1966249
  • Title

    A Compact Fully Integrated High-Efficiency 5GHz Stacked Class-E PA in 65nm CMOS Based on Transformer-Based Charging Acceleration

  • Author

    Chen, Jian ; Bhat, Ritesh ; Krishnaswamy, Harish

  • Author_Institution
    Dept. of Electr. Eng., Columbia Univ., Columbia, NY, USA
  • fYear
    2012
  • fDate
    14-17 Oct. 2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Device stacking enables CMOS power amplifiers (PAs) to increase the maximum achievable output voltage swing by sharing the voltage stress across multiple stacked devices, leading to higher output power and efficiency. A key requirement in stacked class-E power amplifiers is the creation of class-Elike voltage swings at the intermediary nodes. In this paper, we propose a transformer-based charging acceleration technique for stacked class-E PAs. Specifically, in a 2- stacked class-E PA, a shunt inductor is connected at the intermediary node and is magnetically coupled to the choke inductor. When compared with the conventional approach of using an uncoupled shunt inductor, the transformer-based charging acceleration approach significantly reduces the sizes of both inductors and also eliminates the extra area of the shunt inductor through vertical stacking of the windings. Because of the reduced inductor sizes, the associated loss is also reduced leading to an improvement in efficiency of approximately 7% for the 5GHz prototype described here. The differential 5GHz class-E prototype is fabricated in a standard 65nm low-power (LP) CMOS process (IBM 10LPe), and achieves a drain efficiency of 42% and an output power of 19.7dBm while consuming only 0.31mm2 of chip area.
  • Keywords
    CMOS analogue integrated circuits; microwave integrated circuits; microwave power amplifiers; power transformers; transformer magnetic circuits; transformer windings; CMOS PA; CMOS power amplifier; IBM 10LPe; choke inductor; compact fully integrated high-efficiency stacked class-E PA; drain efficiency; efficiency 42 percent; frequency 5 GHz; intermediary node; magnetic coupling; maximum achievable output voltage swing; multiple stacked device; size 65 nm; standard LP CMOS process; standard low-power CMOS process; transformer-based charging acceleration technique; uncoupled shunt inductor; vertical winding stacking; voltage stress; Acceleration; CMOS integrated circuits; Couplings; Inductors; Integrated circuit modeling; Power generation; Radio frequency;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Compound Semiconductor Integrated Circuit Symposium (CSICS), 2012 IEEE
  • Conference_Location
    La Jolla, CA
  • ISSN
    1550-8781
  • Print_ISBN
    978-1-4673-0928-8
  • Type

    conf

  • DOI
    10.1109/CSICS.2012.6340115
  • Filename
    6340115