Feedback processing in fast timing simulation on a multiprocessor system

The implementation of feedback processing techniques in waveform-relaxation-based fast timing simulation on a shared-memory multiprocessor system is presented. A multilevel partitioning technique is applied to the circuit similar to a hierarchical interconnection specification. This multilevel partitioning presents unique problems in its multiprocessor implementation in order to achieve efficient use of processors, especially when simulation activity occurs at various levels in the partitioning. A number of feedback processing techniques have been implemented in a fast timing simulator, IDSIM2, to run on an ALLIANT FX/8 shared-memory computer. A comparison of these techniques when applied to typical examples is presented