Short channel effects and delay hysteresis for 0.25 /spl mu/m SOI technology with minimal process changes from the bulk technology

Partially depleted (PD) SOI technology has been suggested as a method for achieving high performance at low voltage and low power for next generation circuit technologies, but recent results call into question the performance improvement that can be obtained with PD-SOI devices. An important issue is how to modify a baseline bulk process flow to achieve high performance SOI and bulk technology with minimal process changes. A single process flow for both PD-SOI and bulk MOS transistors is described in this paper. The performance of these devices is evaluated in terms of threshold voltage, drive current, off-current, delay times and power. In general, minimal process changes, like adjusting the threshold voltage implant dose, might be required so that the SOI transistor meets the I/sub off/ specification. SOI devices show improved short-channel behaviour and this is supported by process and device simulation. Minimal variation in delay due to floating body induced hysteresis is demonstrated.