Latent failures due to ESD in CMOS integrated circuits

A review is presented of the current information published on the subject of ESD (electrostatic discharge) latent failures. In order to gain a better understanding of the phenomena involved in the input and output protection networks of CMOS integrated circuits, a series of measurements was performed on both commercially available integrated circuits and a set of custom designed and fabricated devices. The tests investigated the effects of electrical stress, thermal shock, exposure to visible and ultraviolet light, and thermal annealing. The results demonstrate the presence of latent failures in CMOS integrated circuits following exposure to ESD. The cumulative effect of repeated discharges can be partially alleviated using thermal annealing or exposure to light. A charge injection model is proposed to interpret the results.<>