DocumentCode :
1966455
Title :
A high-PSR LDO using a feedforward supply-noise cancellation technique
Author :
Yang, Bangda ; Drost, Brian ; Rao, Sachin ; Hanumolu, Pavan Kumar
Author_Institution :
Sch. of EECS, Oregon State Univ., Corvallis, OR, USA
fYear :
2011
fDate :
19-21 Sept. 2011
Firstpage :
1
Lastpage :
4
Abstract :
A feed-forward noise cancellation (FFNC) technique to improve the power supply noise rejection (PSR) of a low dropout regulator (LDO) is presented. The proposed FFNC operates in conjunction with a conventional LDO and extends the noise rejection bandwidth by nearly an order of magnitude. Fabricated in 0.18μm CMOS, at 10mA load current, the prototype achieves a PSR of -50dB and -25dB at 1MHz and 10MHz supply noise frequencies, respectively. Compared to a conventional LDO, this represents an improvement of at least 30dB at 1MHz and 15dB at 10MHz. The prototype uses only 20pF load capacitance and occupies an active area of 0.04mm2.
Keywords :
CMOS integrated circuits; voltage regulators; CMOS process; FFNC technique; capacitance 20 pF; current 10 mA; feedforward supply-noise cancellation technique; frequency 1 MHz; frequency 10 MHz; high-PSR LDO; load capacitance; low dropout regulator; noise figure -25 dB; noise figure -50 dB; noise rejection bandwidth; power supply noise rejection; size 0.18 mum; supply noise frequency; Bandwidth; Calibration; Capacitors; Gain; Noise; Voltage control; Voltage measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2011 IEEE
Conference_Location :
San Jose, CA
ISSN :
0886-5930
Print_ISBN :
978-1-4577-0222-8
Type :
conf
DOI :
10.1109/CICC.2011.6055409
Filename :
6055409
Link To Document :
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