Title :
A 1.3 cycle lock time, non-PLL/DLL jitter suppression clock multiplier based on direct clock cycle interpolation for "clock on demand"
Author :
Saeki, T. ; Mitsuishi, M. ; Iwaki, H. ; Tagishi, M.
Author_Institution :
NEC Corp., Kawasaki, Japan
Abstract :
A 1.3-cycle lock time, jitter suppression clock multiplier based on direct clock cycle interpolation uses an array of short-circuit-current-suppression interpolators. The circuits are verified in 622 MHz clock and data recovery satisfying the ITU-T G.958 jitter tolerance specification.
Keywords :
clocks; interpolation; timing jitter; 622 MHz; ITU-T G.958 specification; clock multiplier; clock on demand; clock recovery; data recovery; direct clock cycle interpolation; jitter suppression; lock time; nonPLL/DLL circuit; short circuit current suppression interpolator; Capacitors; Circuits; Clocks; Delay; Detectors; Error correction; Frequency; Interpolation; Jitter; Timing;
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-5853-8
DOI :
10.1109/ISSCC.2000.839733
