DocumentCode
1966475
Title
An investigation of the performance of a distributed functional digital simulator
Author
Chawla, Praveen ; Carter, Harold W. ; Wilsey, Philip A.
Author_Institution
Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA
fYear
1989
fDate
14-16 Aug 1989
Firstpage
470
Abstract
The performance results for a distributed, multilevel functional digital simulator are presented. The interprocessor synchronization mechanism for the simulator is derived from the virtual time algorithm. Initial studies demonstrate that simulations using n processors execute 0.80 n to 0.95 n times faster than a uniprocessor implementation
Keywords
circuit analysis computing; digital simulation; multiprocessing systems; performance evaluation; synchronisation; digital system design; distributed functional digital simulator; interprocessor synchronization mechanism; multilevel simulator; performance study; virtual time algorithm; Analytical models; Circuit simulation; Computational modeling; Computer simulation; Digital systems; Hardware; Multiprocessing systems; Parallel processing; Switches; Virtual prototyping;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on
Conference_Location
Champaign, IL
Type
conf
DOI
10.1109/MWSCAS.1989.101893
Filename
101893
Link To Document