A time-domain latch interpolation technique for low power flash ADCs

Author

Kim, Jong-In ; Kim, Wan ; Sung, Barosaim ; Ryu, Seung-Tak

Author_Institution

Dept. of EE, KAIST, Daejeon, South Korea

fYear

2011

fDate

19-21 Sept. 2011

Firstpage

1

Lastpage

4

Abstract

A Time-domain latch interpolation technique is presented for low power flash analog-to-digital converter (ADC). The proposed technique reduces the number of first stage latches by half, and thus, reduce power consumption and hardware complexity. A prototype 6bit 1GS/s flash ADC was designed for concept proof in a 90nm CMOS process. The first stage comparators are calibrated by adjusting body voltages. The ADC core consumes 24mW at 1.2V supply. The measured INL and DNL are 0.55LSB and 0.6LSB, respectively after calibration. The SNDR and SFDR are 32.56dB and 43.53dB at 1GS/s with a 50MHz input.

Keywords

CMOS integrated circuits; analogue-digital conversion; interpolation; low-power electronics; time-domain analysis; CMOS process; analog-to-digital converter; concept proof; first stage comparators; frequency 50 MHz; hardware complexity reduction; low power flash ADC; power 24 mW; power consumption reduction; size 90 nm; time-domain latch interpolation technique; voltage 1.2 V; word length 6 bit; CMOS integrated circuits; Calibration; Interpolation; Latches; Preamplifiers; Prototypes; Time domain analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference (CICC), 2011 IEEE

Conference_Location

San Jose, CA

ISSN

0886-5930

Print_ISBN

978-1-4577-0222-8

Type

conf

DOI

10.1109/CICC.2011.6055410

Filename

6055410