Title :
An eight channel 35 GSample/s CMOS timing analyzer
Author :
Weinlader, D. ; Ron Ho ; Chih-Kong Keng Yang ; Horowitz, M.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
While today´s test systems measure inputs at a single time point each cycle, measuring when the inputs arrive is often more useful for understanding timing and jitter problems. An eight channel system is used to explore the feasibility of such a time measuring tester front-end. This system achieves 27.8 ps timing resolution in a 0.25 /spl mu/m CMOS technology using an oversampled architecture with 40 phase-shifted clocks that span a 900 MHz cycle. The chip contains two clock generators, eight input channels, on-chip memory and histogram hardware.
Keywords :
CMOS integrated circuits; timing circuits; 0.25 micron; 27.8 ps; 900 MHz; CMOS timing analyzer; clock generator; histogram hardware; jitter; multichannel system; on-chip memory; oversampling architecture; test system; time measurement; Clocks; Counting circuits; Delay; Histograms; Phase locked loops; Phased arrays; Semiconductor device measurement; System testing; Time measurement; Timing jitter;
Conference_Titel :
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-5853-8
DOI :
10.1109/ISSCC.2000.839735
