Title :
A 2GHz Digital PLL, with temperature lock range of −40°C to 125°C, in 45nm CMOS
Author :
Chattopadhyay, Biman ; Kamath, Anant S. ; Evani, Satyasai ; Subburaj, Karthik
Author_Institution :
Analog, Interconnect & Sub-Syst., Texas Instrum. India Pvt. Ltd., Bangalore, India
Abstract :
A 2GHz, ring-oscillator based Digital PLL (DPLL) with temperature lock range of -40°C to 125°C is presented here. The Digitally Controlled Oscillator (DCO) of the DPLL consists of a current mode Digital to Analog Converter (DAC) followed by a Current Controlled Oscillator (ICO). The current mode DAC is designed such that the outputs of any two adjacent current elements can be progressively brought out for separate ΣΔ operation. This increases the DAC range and hence the DPLL temperature lock range, even as the ΣΔ step size and range are kept small to minimize jitter. The DPLL achieves a phase noise of -90dBC/Hz at 1MHz offset for 2GHz operation. It supports an input frequency range of 0.5MHz to 50MHz, occupies a core area of 0.09mm2 and consumes 7.2mW.
Keywords :
CMOS digital integrated circuits; UHF integrated circuits; digital phase locked loops; digital-analogue conversion; ΣΔ step size; current controlled oscillator; current mode digital to analog converter; digitally controlled oscillator; frequency 0.5 MHz to 50 MHz; frequency 2 GHz; power 7.2 mW; ring-oscillator based digital PLL; size 45 nm; temperature -40 degC to 125 degC; temperature lock range; Jitter; Phase locked loops; Phase noise; Silicon; Temperature distribution;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2011 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4577-0222-8
DOI :
10.1109/CICC.2011.6055413
