Active GHz clock network using distributed PLLs

Most modern microprocessors use a balanced tree to distribute the clock. However, at gigahertz clock speeds an increasing fraction of skew and jitter comes from random variations in gate and interconnect delay. The majority of jitter in a clock tree is introduced by buffers and inter-line coupling to the clock wires. A relatively small amount comes from noise in the source oscillator. This distributed clock network generates the clock signal with phase locked loops (PLLs) at multiple points (nodes) across a chip, and distributes each only to a small section of the chip (tile). Phase detectors (PD) at the boundaries between tiles produce error signals that are summed by an amplifier in each tile and used to adjust the frequency of the node oscillator.