DocumentCode
1966583
Title
Clock generation and distribution for the first IA-64 microprocessor
Author
Rusu, S. ; Tam, S.
Author_Institution
Intel Corp., Santa Clara, CA, USA
fYear
2000
fDate
9-9 Feb. 2000
Firstpage
176
Lastpage
177
Abstract
Increased functionality and performance in today´s microprocessors has resulted in a trend toward larger die sizes and higher operating frequencies. These factors, coupled with larger on-die variations at reduced device geometries, call for special management of the clock distribution skew. The clock generation and distribution for the first IA-64 microprocessor achieves a low skew by using distributed programmable deskew units. Local skew control compensates for load mismatches and within-die process variations, as well as temperature and voltage gradients. In addition, this design supports debug features including on-die clock shrink and test access port (TAP) control of the deskew settings.
Keywords
clocks; microprocessor chips; IA-64 microprocessor; clock distribution; clock generation; distributed programmable deskew unit; skew control; Circuits; Clocks; Delay lines; Detectors; Digital control; Frequency; Microprocessors; Phase detection; Phase locked loops; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-5853-8
Type
conf
DOI
10.1109/ISSCC.2000.839738
Filename
839738
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