A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS

A 1.2 V 12-bit 150 MS/s pipelined ADC with low-gain op-amps (DC gain ≈15 dB) is fabricated in a 65-nm CMOS process. The proposed 5-transistor single stage op-amp enables simple analog circuit to achieve low power and high speed. Digital background calibration technique is exploited to compensate the inter-stage gain error, capacitor mismatch and op-amp nonlinearity. The ADC achieves a peak SNDR of 68 dB and 67 dB and a peak SFDR of 85 dB and 81 dB with 6 MHz input at 100 MS/s and 150 MS/s, respectively. The ADC analog core occupies 0.78 mm² and dissipates 36 mW at 150 MHz sampling rate from a 1.2-V supply. The digital calibration circuit occupies 0.21 mm² and dissipates 12 mW at a clock frequency of 150MHz by estimation with software. The ADC shows a FoM of 194 fJ/conv-step at 150-MS/s from a 1.2-V supply.