A 0.5-V data-storage circuit for triple-threshold MTCMOS/SIMOX LSIs

Summary form only given. 0.5 V CMOS circuit technology on ultra-thin-film SOI provides low-voltage operation without any sacrifice of speed, making it the most effective candidate for ultra-low-power applications in future ULSIs. We have proposed various multi-threshold CMOS/SIMOX (MTCMOS/SIMOX) circuits (Douseki et al. 1996; Fujii et al, 1998) that operate at an ultra-low supply voltage of less than 0.5 V. A triple-V/sub th/ MTCMOS/SIMOX circuit, which combines fully-depleted low- and medium-V/sub th/ CMOS logic gates and partially-depleted high-V/sub th/ power-switch transistors, makes possible fast operation in the active mode and leakage current reduction in both active and sleep modes. An advantage of the circuit is that all combinational logic gates in the conventional CMOS circuit can be easily replaced. However, upon replacing the sequential circuits, there are cases when an additional data-storage circuit is needed in order to store data in the sleep mode. The additional circuit in the critical path affects the speed in the active mode. In this paper, we describe a data-storage circuit that has the additional medium-V/sub th/ circuit in the noncritical path and does not result in any loss of speed.