Device verification tests for high speed analog to digital converters used in satellite communication systems

This paper presents a step-by-step sequence of operations for dynamic performance testing of a high-speed analog-to-digital converter (ADC) using on-chip digital de-multiplexing and clock distribution. Demultiplexed digital outputs are post processed and fed into a computer-aided ADC performance characterization tool. The methodology described reduces test costs and overcomes many test hardware limitations. The problems of high sampling rate ADC testing are described. As our focus is on RF communication system applications, we emphasize the measurement of inter-modulation distortion (IMD) and effective resolution bandwidth (ERB). As Fourier analysis is an important component of characterization, we address the issue of automated sample window adjustment to eliminate leakage and false spur generation. A 6-bit 800 MSamples/s dual channel SiGe based ADC is used as a target example.