DocumentCode
1967140
Title
Implementation of 20Gbit/s area-optimization DQPSK precoder employing FPGA
Author
Zhou, Liming ; Lin, Mi ; Zhang, Yangan ; Wang, Gai ; Zhang, Minglun ; Zhang, Jinnan ; Yuan, Xueguang ; Huang, Yongqing
Author_Institution
Key Lab. of Inf. Photonics & Opt. Commun. (BUPT), Minist. of Educ., Beijing, China
fYear
2010
fDate
8-12 Dec. 2010
Firstpage
391
Lastpage
392
Abstract
In this paper, a new model based on an ameliorated Brent Kung (BK) parallel prefix network (PPN) algorithm was proposed and realized in Virtex V FPGA. In the implementation, compute complexity (area) optimization was achieved. 770 slice registers was utilized and which saved 60% logic resources to the before algorithm.
Keywords
field programmable gate arrays; optical modulation; precoding; quadrature phase shift keying; Virtex V FPGA; ameliorated Brent Kung parallel prefix network algorithm; area-optimization DQPSK precoder; bit rate 20 Gbit/s; logic resources; slice registers; Field programmable gate arrays; High speed optical techniques; Integrated optics; Mathematical model; Optical modulation; Optical polarization;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications and Photonics Conference and Exhibition (ACP), 2010 Asia
Conference_Location
Shanghai
Print_ISBN
978-1-4244-7111-9
Type
conf
DOI
10.1109/ACP.2010.5682504
Filename
5682504
Link To Document