An 833 MHz 1.5 W 18 Mb CMOS SRAM with 1.67 Gb/s/pin

Author

Pilo, H. ; Allen, A. ; Covino, J. ; Hansen, P. ; Lamphier, S. ; Murphy, C. ; Traver, T. ; Yee, P.

Author_Institution

IBM Microelectron., Essex Junction, VT, USA

fYear

2000

fDate

9-9 Feb. 2000

Firstpage

266

Lastpage

267

Abstract

The authors present an 18 Mb CMOS SRAM which operates at 833 MHz with 1.67 Gb/s/pin. The 114.4 mm/sup 2/ die consumes 1.5 W and is fabricated in a 0.18 /spl mu/m CMOS process with four levels of copper interconnect. The SRAM operates in two user-selectable double-data-rate modes (DDR and DDR2). High-frequency operation is achieved by solving three frequency-limiting issues identified in previous SRAM designs: managing data timing constraints associated with high-frequency operation in a high density SRAM core; maintaining coherency between SRAM output data timings and echo clock timings; and delivering symmetric data windows for 1 s and 0 s across a wide range of output driver supply levels.

Keywords

CMOS memory circuits; SRAM chips; high-speed integrated circuits; timing; 0.18 micron; 1.5 W; 1.67 Gbit/s; 18 Mbit; 833 MHz; CMOS SRAM; Cu; Cu interconnect; clock timings; data timing constraints; four level interconnect; high density SRAM core; high-frequency operation; symmetric data windows; user-selectable double-data-rate modes; CMOS process; Clocks; Copper; Decoding; Delay; Latches; Microelectronics; Random access memory; Switches; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-5853-8

Type

conf

DOI

10.1109/ISSCC.2000.839778

Filename

839778