5 GHz CMOS radio transceiver front-end chipset

This 5 GHz CMOS radio transceiver front-end chipset for wireless LAN applications incorporates the direct conversion architecture and is implemented in 0.25 /spl mu/m CMOS. The 3 V receiver and transmitter dissipate 114 mW and 120 mW, respectively. External RF band-select filters, a frequency synthesizer and a power amplifier complete the radio front-end. The differential circuit topology is employed throughout both the receiver and transmitter circuits to minimize undesired coupling, especially leakage of the local oscillator (LO) through the mixers to the antenna, as this causes DC offset which corrupts the desired low-frequency signal.