Possibilities and limitations for a fully-digital RF signal synthesis and control [particle accelerators]

Since the advent of VLSI circuits capable of data rates in excess of 30 MWords/s, real time digital RF synthesis has become an interesting and viable avenue to be used with accelerators. This technique builds up RF signals from a real-time sequence of digital words with minimum use of analog components. With digital RF, hitherto not achieved agility, precision, and reproducibility for frequency and phase are now possible. This permits optimum acceleration ramp functions, subject to any desired constraints in longitudinal phase space, as given phase or voltage or acceptance, or yet another bucket quantity. Since phase fidelity is crucial with accelerator applications, a high degree of over-sampling is mandatory, posing the only actual limitation to these new techniques. However, with clock rates of more than 1 GHz, today´s component technology limits the RF carrier to some 10 to about 100 MHz, depending on which signal-to-noise ratio is acceptable. This range can further be extended by means of analog up-conversion. A number of digital RF techniques have been developed at the cooler synchrotron COSY, e.g. for RF acceleration and ultraslow extraction, and were made available also for the acceleration with TSR, Heidelberg. Further possible applications are being explored