PLL subsystem for NSLS booster ring power supplies

A high-performance digital phase-lock loop subsystem has been designed as part of the upgrade to the magnet power supplies in the booster ring at the National Synchrotron Light Source. The PLL subsystem uses a dedicated floating-point digital signal processor to implement the required filters and the startup, fault-handling, and running logic. The subsystem consists of two loops; the first loop tracks long-term changes in the line frequency, while the second tracks more rapid variations. To achieve the required performance, the order of the loop transfer functions was taken to be five, in contrast to the second-or third-order loops usually used. The use of such high-order loops required design techniques different from those normally used for PLL filter design. The hardware and software elements of the subsystem are described, and the design methodology used for the filters is presented. Performance is described and compared to theoretical predictions