Title :
A 128 kb SRAM with soft error immunity for 0.35 /spl mu/m SOI-CMOS embedded cell arrays
Author :
Wada, Y. ; Nii, K. ; Kuriyama, H. ; Maeda, S. ; Ueda, K. ; Matsuda, Y.
Author_Institution :
Syst. LSI Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
Summary form only given. Embedded cell arrays are more suitable for high-performance ASICs rather than gate arrays, because they can integrate high-quality building blocks such as high-density memories and optimized analog circuits together with digital logic circuits. This paper describes a 128 kb synchronous SRAM with body-fixed structure for embedded cell arrays using a 0.35 /spl mu/m SOI-CMOS process. The circuit performance and the soft error rate of the SRAM were measured and compared with those of a 128 kb SRAM with floating-body configuration.
Keywords :
CMOS memory circuits; SIMOX; SRAM chips; cellular arrays; embedded systems; error analysis; integrated circuit design; integrated circuit testing; logic design; logic testing; 0.35 micron; 128 kbit; ASICs; SOI-CMOS embedded cell arrays; SOI-CMOS process; SRAM; Si-SiO/sub 2/; body-fixed structure; circuit performance; digital logic circuits; embedded cell arrays; floating-body configuration; gate arrays; high-density memories; optimized analog circuits; soft error immunity; soft error rate; synchronous SRAM; Board of Directors; Error analysis; MOS devices; Power dissipation; Random access memory; Testing; Threshold voltage;
Conference_Titel :
SOI Conference, 1998. Proceedings., 1998 IEEE International
Conference_Location :
Stuart, FL, USA
Print_ISBN :
0-7803-4500-2
DOI :
10.1109/SOI.1998.723144
